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Dear Subscriber

Much ado has been made in the industry of late about a comment from Intel’s Mark Bohr last month about the fabless model collapsing. Only the IDMs will be able to handle such small and complex devices as the semiconductor arena faces in the coming years, Bohr contended in a recent Q&A. I’m including here one of the most recent commentaries on Bohr’s assertion. What’s your take? Does Bohr have a point, or is he just blowing hot air?

Aaron Hand, Contributing Editor

Fab Simulation and Variability
James P. Ignizio, The Institute for Resource Management; and Hernando Garrido, Fresenius Medical Care
Simulation, specifically discrete event simulation, is widely employed throughout the manufacturing sector—particularly in semiconductor and photovoltaic fabs—for prediction and assessment of factory performance. Of special interest is fab cycle time and capacity. Whether it be a proposed, ramping or mature fab, it is vital to have accurate estimates of facility performance. Conventional wisdom among simulation personnel is that once a detailed fab simulation model has been developed, the model should be run for a period of one to possibly two years of simulated time so as to reach the “steady state” performance of the simulated fab. This process is repeated a number of times and the average of the results is employed in the decision-making process (e.g., should more or fewer tools be used?). Again, conventional wisdom holds that such a process is sufficient to establish accurate estimates of fab performance. That assumption is challenged in this paper. Read More

Applying Quantile Regression to Defect vs. Test Component Bin Correlations
Garry Tuohy, GlobalFoundries
Quantile regression is presented as a practical method for completely describing the relationship between defect inspection data and individual test component bins that is robust against the influence of outlier data points. This is particularly useful in cases where yield variations manifest as changes in a single component bin. It can also complement traditional methods of calculating kill ratios and yield loss. This method is much more computationally intensive than the method of least squares as it does not have a closed-form solution. Various linear algebra-based algorithms have been developed to calculate the quantile regression fits. A purely heuristic algorithm is presented here for this purpose. It is hoped that this paper will help motivate others in the semiconductor industry to explore this analysis technique further. Read More

Winbond Joins ISMI to Develop Productivity Solutions
Sematech, 5/10/2012
Sematech announced that Winbond Electronics has joined the International Sematech Manufacturing Initiative (ISMI) program based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. Winbond will join ISMI and its members to develop innovative manufacturing capabilities to solve common productivity, cost and cycle time challenges in semiconductor factories and equipment. Read More

Eve Becomes Member of Si2
Marketwire, 5/10/2012
Eve, which provides hardware/software co-verification, has become a member of the Silicon Integration Initiative (Si2). By joining Si2, Eve will have an opportunity to work cooperatively with other EDA tool providers on the development and adoption of standards to improve verification methodologies. Read More

Obama Makes Made-in-America Pitch at N.Y. Chip Site
Brooke Crothers, CNET, 5/8/2012
President Obama made a campaign stop at a major chip research and manufacturing hub in New York to reemphasize his made-in-America theme. Obama visited the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. CNSE is an education and research facility centered on nanotechnology. The visit was intended to highlight “insourcing” and the connection between education, innovation and manufacturing in supporting investment and bringing jobs back to the United States. Read More

SIA Applauds House and Senate Appropriations Committees for Supporting Increased Funding for Scientific Research
SIA, 5/7/2012
The Semiconductor Industry Association (SIA) applauded the House of Representatives and the Senate Appropriations Committees’ support for increased funding levels for both the National Science Foundation (NSF) and the National Institute of Standards and Technology (NIST). Through highly effective and successful public-private partnerships with the semiconductor industry, NSF and NIST enable research that will significantly advance semiconductor innovations, affecting a number of downstream industries that rely on semiconductor technology for growth and advancement. Read More

CEA-Leti Unveils Wide-Reaching Silicon Research Scope
Solid State Technology, 5/2/2012
CEA-Leti has introduced the “LETI-3S” concept, for “Silicon Specialty Solutions.” The research is oriented to startups, component integrators, fabless or fablite chip companies, and equipment/consumable suppliers. Other potential partners include foundries, research centers with a limited process offer, micro and nanotechnologies companies that do not want low-volume activities, and high-value silicon wafer suppliers. 3S addresses deposition; front side/back side clean, wet etch and strip; lithography with dual side alignment capability; etching, implant, epitaxy, diffusion; chemical mechanical polishing (CMP), bonding, grinding, dicing; and advanced inline metrology. Read More

Reversal From the Foundry Model Back to IDM?
Zvi Or-Bach, MonolithIC 3D, EE Times, 5/11/2012
Recently Rick Merritt of EE Times reported on his interview with Mark Bohr, “Mr. Process Technology at Intel,” and wrote: “It’s the beginning of the end for the fabless model, according to Mark Bohr.” Quite naturally this caused many responses, with the majority of them hinting that Intel is trying to break into the smart mobile space by sowing doubt in the future of the existing ecosystem around TSMC-ARM and multiple fabless vendors. In light of recent reports, are we facing a dramatic reversal of the trend from the foundry model back to the IDM model? Read More

Microsoft Joins Micron Memory Cube Effort
Rick Merritt, EE Times, 5/8/2012
Microsoft became the seventh core member of the Hybrid Memory Cube Consortium led by Micron and Samsung, a sign of the broad technical implications for the concept of 3D memory chip stacks. Microsoft’s participation signals the potential of the Memory Cube to drive changes in the traditional memory hierarchy and systems software for computers and networks. Micron has proposed a cube of stacked memory die that includes a logic layer to optimize the placement of and access to memory, potentially handling functions carried out by memory controllers typically integrated in server and network processors today. Read More

III-V Lab Shares Silicon and Compound Semiconductor Work 1 Year In
Solid State Technology, 5/7/2012
III-V Lab, a joint lab of Alcatel-Lucent Bell Labs France, Thales Research and Technology and CEA-Leti, provides an update one year into its four main research area projects. In an effort to bring the performance benefits of III-V components onto silicon CMOS platforms, the partnership leverages the different expertise and know-how of the organizations in optoelectronics, microelectronics and heterogeneous integration, to innovate in four primary areas of research and markets. After a year, the III-V Lab has already enabled the rapid development of a common platform for optoelectronic and microelectronic technology. Read More

Organic Complementary Logic Aim of 2 European Research Projects
Solid State Technology, 5/4/2012
The Heterogeneous Technology Alliance (HTA), a team of European technology institutes, is focusing on high-performance organic electronic circuits through two projects: COSMIC to develop p- and n-type organic thin film transistors (OTFTs) for complementary logic, and POLARIC for shrinking critical dimensions (CDs) of OTFTs. Read More

Emerging Memories Take Stage at VLSI Symposium
David Lammers, Semiconductor Manufacturing & Design, 5/2/2012
The 2012 Symposia on VLSI Technology & Circuits, planned for mid-June in Honolulu, points to future directions in memory technology, including 3D NAND, spin torque transfer MRAM, ferroelectric memories, and other emerging memory types. Intel’s K. Zhang will give an invited paper on SRAMs using tri-gate transistors. A team from GlobalFoundries, the Fraunhofer Center of Nanoelectronic Technologies, and NaMLab will describe progress with ferroelectric materials for non-volatile memories that consume less power than other new memory types. The team has created the “most aggressively scaled” FeFETs using ferroelectric Si:HfO2 in a 28 nm high-k/metal gate stack. Read More

Exeter Researchers Come Up With Possible ITO Replacement
Nicolas Mokhoff, EE Times, 5/2/2012
A research team from the University of Exeter has placed its stamp on its unique version of a transparent, lightweight and flexible graphene material. To create what they call GraphExeter, the Exeter team sandwiched molecules of ferric chloride between two layers of graphene. Ferric chloride enhances the electrical conductivity of graphene, without affecting the material’s transparency. GraphExeter is said to be much more flexible than indium tin oxide, the main conductive material currently used in electronics. The increasingly expensive ITO is expected to run out in 2017. Read More

GlobalFoundries, Infineon, IBM, ST Linked to Indian Fab Plan
Peter Clarke, EE Times, 5/1/2012
More companies are being linked to the Indian government’s plan to get one or more semiconductor wafer fabs constructed on the subcontinent. At least five chip companies have expressed an interest in supporting the project, according to a Hindu Business Line report. The five are GlobalFoundries, Infineon Technologies, STMicrolectronics, Russia’s Sitronics JSC, and a consortium comprising Jaypee Associates, IBM and Tower Semiconductor, the report said without naming sources. Sitronics is the parent of Mikron JSC (Zelenograd, Russia), Russia’s leading IC manufacturer. Read More




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 Imec Technology Forum 2012
May 22-24, 2012
Brussels, Belgium 
At ITF2012, you will meet an exciting mix of renowned industrial speakers, imec executives and top researchers. You will get an early insight in market trends and evolutions in nanoelectronics, healthcare, smart vision and communication systems and energy. ITF2012 is the ideal networking place to meet key players from industry, research institutes and policy makers to discuss how to keep abreast in a fast changing economy and make your nanoelectronics-based business a sustainable one. Click here for more information. 

SEMATECH Workshop on 3D Interconnect Metrology
July 11, 2012
San Francisco, CA
Successful introduction of 3D interconnects will require that equipment suppliers and device manufacturers overcome the inherent challenges associated with measuring opaque films and high-aspect ratio features that dominate 3D architectures. You are invited to join other industry experts from around the world to address these issues at the SEMATECH Workshop on 3D Interconnect Metrology to be held July, 2012 in conjunction with SEMICON West. Click here for more information.

Test Vision 2020
July 11-12, 2012
Marriott Marquis, San Francisco, CA
Test Vision 2020, formerly ATE Vision, has emerged as the premier workshop in the area of Automated Test Equipment. Attracting record attendance from a broad cross-section of the semiconductor community, the workshop features a compelling line-up of papers, keynotes and panel participation from leaders in the industry. This year, once again the workshop will be held with SEMICON West and will examine where the test industry is heading and provide a forum for discussing the directions and solutions for emerging problems. Click here for more information.

SEMATECH International Symposium on Advanced Gate Stack Technology
Oct. 3-4, 2012
Saratoga Springs, NY

This year, the symposium will focus on Advances in Non-Volatile Memory and Non-Si Device Technology.The symposium will feature experts from industry and academia presenting their latest research in both invited and contributed talks, and a discussion panel of representatives from major semiconductor device makers, equipment makers, and universities. Click here for more information.

Integrated Circuit Fabrication and Yield Control
Oct. 9-10, 2012
Albany, NY
Learn the basics of chip fabrication from an expert - from basic transistors to step-by-step build sequences - at CNSE, the world's #1 college for nanotechnology! This two-day course is ideal for engineers, technicians, sales persons, account managers, executives and others who need basic fabrication knowledge and perspective to deal effectively with customers and make informed decisions. Click here for more information.

2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics
March 25-28, 2013
Gaithersburg, Maryland
This conference, the ninth in the series, will focus on the frontiers and innovation in characterization and metrology of nanoelectronics. It is sponsored by the National Institute of Standards and Technology, College of Nanoscale Science and Engineering, CEA-LETI, Semiconductor Research Corporation (SRC), International SEMATECH Manufacturing Initiative (ISMI), AVS, National Science Foundation (NSF), American Physical Society (APS), and IEEE/Electron Devices Society. Click here for more information.


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